DDR.CHIP.EVOLUTION
Main memory generations · per DRAM device · 2000–2028 scenario

DDR capacity grew by bits. Bandwidth grew by edges.

This report normalizes DDR generations to a single memory chip, using an x8 DRAM device for bandwidth. It separates real JEDEC-era milestones from the still-unfinalized DDR6 target so the next-generation point does not masquerade as settled fact.

capacity
32×
JEDEC scoped per-chip density: DDR 1 Gb → DDR5 32 Gb.
bandwidth
22×
x8 chip peak bandwidth: 0.4 GB/s → 8.8 GB/s.
DDR6
17.6
GB/s per x8 chip if the high-end DDR6 target becomes standard.
definition
x8
Commodity device width used for apples-to-apples per-chip bandwidth.

Capacity per chip: the density ladder.

Capacity is total storage in one DRAM device, shown in gigabits. Divide by 8 for gigabytes. The DDR6 point is a scenario marker, not a JEDEC-published limit.

Bandwidth per chip: data rate × pins.

For an x8 chip, GB/s is numerically equal to MT/s ÷ 1000. Plotly buttons let you compare x4, x8 and x16 devices.

Per chip is not per DIMM.

A normal 64-bit DIMM rank uses multiple DRAM chips in parallel. Module bandwidth is therefore the aggregate of chips, ranks, channels, controller policy and clocking.

Gb/s, MT/s and GB/s.

DDR marketing speed is usually transfers per second per pin. For x8 chips: MT/s × 8 bits ÷ 8 = MB/s.

x8 GB/s = MT/s ÷ 1000

DDR5 has a late-life kink.

The 2025 DDR5D-era update creates a visible bandwidth step without a matching JEDEC density-scope step: faster edge rates, same 8–32 Gb device scope.

The one-chip envelope.

This bubble plot puts capacity and x8 bandwidth together. Up/right is better; bubble area also scales with capacity.

Data table and assumptions.

The table is intentionally standards-first. Where the public record is fuzzy, the row is labeled as an update or projection rather than treated as ordinary history.

YearGenerationMilestoneDevice capacityData ratex8 chip bandwidthStatusNotes

Sources and caveats

  1. JEDEC JESD79F: DDR SDRAM scope, 64 Mb through 1 Gb devices with x4/x8/x16 interfaces.
  2. JEDEC JESD79-2F: DDR2 SDRAM scope, 256 Mb through 4 Gb devices with x4/x8/x16 interfaces.
  3. JEDEC DDR3 publication, June 2007: 800–1600 MT/s and 512 Mb through 8 Gb densities.
  4. JEDEC JESD79-4 family: DDR4 scope, 2 Gb through 16 Gb devices; DDR4-3200 ceiling used for the bandwidth normalization.
  5. JEDEC DDR5 publication, July 2020: DDR5 launch at 4.8 Gb/s and double DDR4 bandwidth direction.
  6. JEDEC JESD79-5D: DDR5 scope, 8 Gb through 32 Gb devices with x4/x8/x16 interfaces.
  7. JEDEC Main Memory focus area: DDR6 is still in development in JC-42; DDR5D update noted for November 2025.
  8. DDR6 bandwidth targets are from industry reporting around JEDEC roadmap discussions, commonly citing roughly 8.8–17.6 Gb/s. Treat the plotted DDR6 point as a forward scenario until JEDEC publishes the standard.
Generated 2026-05-27 20:22 ICTPlotly report · IBM Carbon-inspired visual system · normalized x8 device model